Power Optimized Full Adder Architecture
نویسنده
چکیده
In most of the digital systems the full-adders are the basic and the fundamental components. Due to the increase in number of transistors on the chip and its shrinkage has made the power consumption to be more. This power consumption is due to the flow of current and causes the battery life to be reduced. Hence the need of low power designs is the primary requirement in the VLSI field. The full adders are used for many purposes namely multiplication, subtraction, parity checking, large addition and so on. Improving the Full-adder circuit can reduce the power consumption to the larger extent in the system level. In this paper we have proposed a full-adder circuit that consumes the lesser power compared to other adder. The 1bit Full Adder has been designed in the Tanner tool V 13.1 and modelled to 250nm technology by considering all the cases for the input vectors. Keywords-VLSI, Digital Systems, Full Adder, Power Consumption
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